Analog circuits typically display sensitivity to excessive voltage levels. Transients, such as electrostatic discharges (ESD) can therefore cause the voltage handling capabilities of the analog circuit to be exceeded, resulting in damage to the analog circuit. In order to protect circuits during ESD events, clamps have been devised to shunt current to ground during excessive voltage peaks.
One of the difficulties encountered in designing such protection circuitry is that the specifications for these clamps have to fit within a relatively small design window that, on the one hand, must take into account the breakdown voltage of the circuit being protected, and, on the other hand, avoid latch-up under normal operation. Thus, the clamp must be designed so as to be activated below the breakdown voltage of the circuit that is to be protected. At the same time, the latch-up or holding voltage must exceed the normal operating voltage of the protected circuit.
Different protection devices have been developed, each with certain strengths and weaknesses. For instance, grounded gate NMOS devices (GGNMOS) have a high holding voltage but are large and support only limited current densities.
Silicon-controlled rectifiers (SCRs) and low voltage silicon controlled rectifiers (LVTSCRs) on the other hand support higher current densities but suffer from low holding voltage, making them susceptible to latch-up. These characteristics are best understood by considering the double injection process that takes place during the triggering of SCRs and LVTSCRs.
FIG. 1 shows a cross-sectional diagram that illustrates a conventional LVTSCR 100. The LVTSCR 100 has a n-well 112 formed in a p-type material 110. n+ and p+ regions are formed in each of the n-well 112 and the p-material 110. In the case of the n-well well 112 the regions include n+ region 114 and p+ region 116. For the p-material 110, the regions are n+ region 122 and p+ region 124. Furthermore, a n+ (floating drain) region 130 is formed in both material 110 and n-well 112, and a channel region 132 is defined between n+ (source) region 122 and n+ (floating drain) region 130. In addition, LVTSCR 100 includes a gate 136. N+ (source and floating drain) regions 122, 130, and gate 136 define a NMOS transistor 138 which is typically formed to be identical to the to-be-protected MOS transistors in the circuit.
In operation, when the voltage on the drain of a conventional NMOS transistor spikes up, the drain-to-substrate junction of the NMOS transistor breaks down, for example, at 7 volts, while the gate oxide layer that isolates the gate from the drain destructively breaks down at, for example, 10-15 volts.
Since NMOS transistor 138 is formed to be identical to the to-be-protected MOS transistors, the junction between n+ region 130 and material 110 breaks down at the same time that the to-be-protected MOS transistors experience junction breakdown, thereby preventing destructive breakdown of the MOS transistors that are being protected.
In operation, when the voltage across node 120 (low voltage node) and 126 (high voltage node) is positive and less than the trigger voltage, the voltage reverse biases the junction between n-well 112 and p-type material 110. The reverse-biased junction, in turn, blocks charge carriers from flowing from node 120 to node 126. However, when the voltage across nodes 120 and 126 is positive and equal to or greater than the trigger voltage, the reverse-biased junction breaks down due to avalanche multiplication.
The breakdown of the junction causes a large number of holes to be injected into material 110, and a large number of electrons to be injected into n-well 112. The increased number of holes increases the potential of material 110 in the region that lies adjacent to n+ region 122, and eventually forward biases the junction between material 110 and n+ region 122.
When the increased potential forward biases the junction, a npn transistor that utilizes n+ region 122 as the emitter, p-type material 10 as the base, and n-well 112 as the collector turns on. When turned on, n+ (emitter) region 122 injects electrons into (base) material 110. Most of the injected electrons diffuse through (base) material 110 and are swept from (base) material 110 into (collector) n-well 112 by the electric field that extends across the reverse-biased junction. The electrons in (collector) n-well 112 are then collected by n+ region 114.
A small number of the electrons injected into (base) material 110 recombine with holes in (base) material 110 and are lost. The holes lost to recombination with the injected electrons are replaced by holes injected into (base) material 110 by the broken-down reverse-biased junction and, as described below, by the collector current of a pnp transistor, thereby providing the base current.
The electrons that are injected and swept into n-well 112 also decrease the potential of n-well 112 in the region that lies adjacent to p+ region 116, and eventually forward bias the junction between p+ region 116 and n-well 112. When the decreased potential forward biases the junction between p+ region 116 and n-well 112, a pnp transistor formed from p+ region 116, n-well 112, and material 110, turns on.
When turned on, p+ emitter 116 injects holes into base 112. Most of the injected holes diffuse through (base) n-well 112 and are swept from (base) n-well 112 into (collector) material 110 by the electric field that extends across the reverse-biased junction. The holes in (collector) material 110 are then collected by p+ region 124.
A small number of the holes injected into (base) n-well 112 recombine with electrons in (base) n-well 112 and are lost. The electrons lost to recombination with the injected holes are replaced by electrons flowing into n-well 112 as a result of the broken-down reverse-biased junction, and n-well 112 being the collector of the npn transistor. Thus, a small part of the npn collector current forms the base current of the pnp transistor.
Similarly, as noted above, the holes swept into (collector) material 110 also provide the base current holes necessary to compensate for the holes lost to recombination with the diffusing electrons injected by n+ (emitter) region 122. Thus, a small part of the pnp collector current forms the base current of the npn transistor.
Thus, n+ region 122 injects electrons that provide both the electrons for the collector current of the npn transistor as well as the electrons for the base current of the pnp transistor. At the same time, p+ region 116 injects holes that provide both the holes for the collector current of the pnp transistor as well as the holes for the base current of the npn transistor.
This is injection of both holes and electrons is referred to as double injection and provides current densities (after snapback) that are about ten times greater than the densities provided by a grounded-gate MOS device. Since junction break down occurs before the MOS transistors experience destructive gate oxide break down, LVTSCR 100 turns on before destructive gate oxide breakdown occurs, thereby protecting the MOS transistors. Thus, the junction breakdown voltage, which is less than the voltage level that causes destructive gate oxide breakdown, functions as the trigger voltage.
However, as mentioned above, one disadvantage of LVTSCR 100, and, for that matter, any SCR is that it suffers from a holding voltage that is often less than the minimum (or latch-up) voltage of the ESD protection window. The low holding voltage of the LVTSCR which lies in the range of less than two volts, is due to the double junction injection of its conductivity modulation mechanism. While the p+ emitter allows one to define how many holes are injected, the injection of the holes leads to greater space charge neutralization and thus a lower holding voltage. This creates a problem when seeking to protect circuits that are biased above a certain voltage, such as circuits biased above 2V, since it causes latch-up in the LVTSCR.
Furthermore, the LVTSCR is limited in its use as a self-protection device since the through n-well connection between the contacted drain region 114 and the floating drain 130 displays unacceptably high n-well resistance for normal operation, causing reduced saturation current
What is needed is a compact solution to the problem wherein the LVTSCR has a higher holding voltage characteristic.